1. Field of the Invention
The present invention generally relates to the field of semiconductor manufacturing and, more particularly, to a wafer level package (WLP) with improved interconnection reliability and a method for manufacturing the same.
2. Description of the Related Art
In order to meet ever-demanding packaging requirements for newer generations of electronic products, countless efforts have been expended to create the most reliable, cost-effective, small, and high- performance packages. Such requirements are, for example, reductions in propagation delay and in overall component area as well as broader latitude in input/output (I/O).
To meet those requirements, a wafer level package (WLP) has been recently developed. In the WLP, unlike the periphery leaded packages, an array of external terminals is distributed over the semiconductor surface in place of outer leads of leaded packages. This reduces the signal path from a semiconductor chip to package I/O location, thereby improving the electrical performance of the device. Further, the area it occupies when mounted onto a printed circuit board or other substrate is the size of the chip. Thus, the size of the WLP is very small.
For these reasons, almost all WLPs use metallic solder balls disposed in an area array fashion to interconnect the package to the printed circuit board.
However, due to grossly mismatched coefficient of thermal expansions (CTE) between the chip and the printed circuit board, if the metallic solder balls, which are minimally elastic, alone were used to interconnect the chip contacts to the substrate, the strain would be absorbed by the solder balls, causing them to crack and fail due to the mechanical stress of the differential CTE of the chip relative to the printed circuit board, thereby damaging the reliability of the solder connection.
In other words, when the chip heats up during use, both the chip and the board expand, and when the heat is removed, both the chip and the substrate shrink. The problem that arises is that the chip and the substrate expand and contract at different rates and at different times, thereby stressing the interconnections or solder balls between them.
Some attempts have been made to solve these problems, but they turned out to be unsuccessful. Moreover, if the chip size becomes large, it has been discovered that the residual stress or displacement at the periphery of the chip also significantly increases compared to that of the center portion of the chip.
As a result, with conventional structures, experience says that it is not sufficient to prevent the solder cracking or the breakage of metal interconnection at the side of the solder ball pad, especially near the edge of the chip.
Therefore, what is needed is a newly designed WLP with improved interconnection reliability, especially between the chip and the board, and a method of manufacturing the same.
The present invention provides a thermal-stress-absorbing interface structure for a WLP and the method of manufacturing the same to improve interconnection reliability of the WLP such as solder joint reliability.
According to preferred embodiments of the present invention, a thermal-stress-absorbing interface structure between a semiconductor integrated circuit chip and a surface-mount structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The thermal-stress-absorbing interface structure further includes means for allowing the first end of the pad to move up when the second end of the pad moves down and alternately allowing the first end to move down when the second end moves up, upon thermal cycling. The means has a center axis. The up-and-down movements of the pad are balanced on the center axis. The interface structure can include a conductive bump formed on the pad.
According one aspect of the present invention, a method of forming a WLP is disclosed. The method comprises providing a semiconductor wafer having a plurality of semiconductor chips and a plurality of scribe lines. Each of the semiconductor chips includes a plurality chip pads and a passivation layer thereon. Then, a multi-layer thermal-stress-absorbing support structure is formed over the resulting structure. Next, a first patterned conductor layer is formed over the multi-layer structure. A first patterned insulation layer is formed over the first patterned conductor layer. Here, the first patterned insulation layer includes an opening therein. The opening exposes a portion of the first patterned conductor layer. Then, a conductive bump is placed over the exposed portion of first patterned conductor layer. Lastly, the wafer is singulated to separate the semiconductor chips to complete the WLP.
Preferably, the multi-layer structure comprises a first polymer layer and a second polymer layer covering the first polymer layer. The first and second polymer layers and the pad including the interconnection line, which extends from the side thereof intermediate the first and the second ends, cooperatively allows the elongated conductive bump pad to make the up-and-down movements pivoted on the center axis and allows the first and second polymers to resiliently deform corresponding to the up-and-down movements of the pad balanced on the center axis, upon thermal cycling. This absorbs or dissipates thermal stresses generated during thermal cycling.
With these features of the present invention, interconnection reliability of the WLP can be significantly improved. For example, the thermal stresses generated during the thermal cycling are absorbed or dissipated efficiently without breakage of the joints (physical connection) between the conductive bump and the underlying structure.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention that proceeds with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view of a thermal-stress-absorbing interface structure in accordance with one embodiment of the present invention.
FIG. 2 is a plan view of an elongated conductive bump pad and an interconnection line extending therefrom in accordance with the preferred embodiment of the present invention.
FIG. 3 is a cross-sectional view of the thermal-stress-absorbing interface structure during various stages of thermal cycling, i.e. heating up and cooling down, to show the up-and-down movement of the pad to absorb a thermal stress.
FIG. 4 is a schematic top view of a semiconductor wafer that includes semiconductor integrated circuit chips and scribe lines formed thereon.
FIG. 5 is a cross-sectional view of a part of the semiconductor substrate with a passivation layer formed thereon exposing chip pads.
FIG. 6 is a cross-sectional view showing a patterned polymeric layer formed overlying the passivation layer shown in FIG. 5.
FIG. 7 is a cross-sectional view showing a patterned metal layer for electrical interconnection between the chip pads and conductive bump pads including a ground metal layer.
FIG. 8A is a cross-sectional view showing a first polymer layer to form a thermal-stress-absorbing interface structure in accordance with preferred embodiment of the present invention.
FIG. 8B is a plan view corresponding to FIG. 8A.
FIG. 9 is a cross-sectional view showing a second polymer layer formed overlying the first polymer layer shown in FIG. 7.
FIG. 10A is a cross-sectional view showing another patterned metal layer for forming a conductive bump pad and an interconnection line extending therefrom as shown in FIG. 2.
FIG. 10B is a plan view of FIG. 10A showing a first patterned conductor layer for forming the conductive bump pad and the interconnection line.
FIG. 11 is a cross-sectional view showing a patterned dielectric layer formed overlying the patterned metal layer shown in FIGS. 10A and 10B.
FIG. 12 is a cross-sectional view showing a conductive bump formed overlying the conductive bump pad.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity.